This invention pertains to microlithography (projection-transfer of a pattern, defined by a reticle or mask, to a sensitive substrate). Microlithography is a key technology used in the manufacture of microelectronic devices such as integrated circuits, displays, micromachines, and the like. More specifically, the invention pertains to microlithography as performed using a charged particle beam (e.g., electron beam or ion beam) as an energy beam.
Microlithography using a charged particle beam (e.g., electron beam or ion beam) offers prospects of better resolution compared to optical microlithography, for reasons similar to the reasons why electron microscopy yields better resolution than optical microscopy. Unfortunately, whereas much optical microlithography is performed using a scheme in which an entire die (chip) pattern, as defined by the reticle, is projection-transferred to a sensitive substrate in one xe2x80x9cshotxe2x80x9d of a light beam, such xe2x80x9cone-shotxe2x80x9d projection-transfer of an entire reticle pattern using charged-particle-beam (CPB) microlithography has not yet been realized. The reasons pertain mainly to the inability to fabricate a suitable reticle that can be exposed in one shot of a charged particle beam, and the inability to fabricate CPB lens systems sufficiently large to project an entire reticle pattern with adequate control of aberrations.
In view of the above, a favored conventional CPB microlithography approach is to divide the reticle into multiple exposure units usually termed xe2x80x9csubfields.xe2x80x9d The subfields are exposed individually by respective xe2x80x9cshotsxe2x80x9d of the beam, and images of the individual subfields are formed on the substrate in locations serving to xe2x80x9cstitchxe2x80x9d the images together to form an integral image of the entire pattern at a respective xe2x80x9cdiexe2x80x9d or xe2x80x9cchipxe2x80x9d on the substrate.
Regarding the substrate, a xe2x80x9csensitivexe2x80x9d substrate is coated on its upstream-facing surface with a suitable xe2x80x9cresist,xe2x80x9d which is a substance that, when exposed to a charged particle beam carrying an image, responds to the exposure by forming a latent image. The substrate usually is sufficiently large to be exposed with multiple chips that usually are placed side-by-side on the substrate in a two-dimensional rectilinear array. The substrate usually is a semiconductor wafer (e.g., silicon wafer), but can be any of various other suitable materials and configurations. Herein, xe2x80x9csubstratexe2x80x9d and xe2x80x9cwaferxe2x80x9d are used interchangeably.
As noted above, the die pattern on the reticle typically is divided into a large number of subfields. The subfields are exposed in an ordered sequence. To such end, the subfields normally are arranged in hierarchical groups. The usual group structure involves xe2x80x9crowsxe2x80x9d and xe2x80x9cstripes,xe2x80x9d wherein a row includes several subfields, and a stripe includes multiple parallel rows. During exposure, the subfields in each row, the rows in each stripe, and the stripes are exposed sequentially. Thus, each die is exposed. Across the wafer, the dies are exposed sequentially, normally in a raster manner.
Reference is made to FIG. 31 depicting an array of chips T (each having dimensions of, e.g., 25xc3x9725 mm) situated on a wafer W (having a diameter of, e.g., 200 mm). Each chip includes five stripes S each comprising multiple rows (not shown) of subfields. Each stripe S has a width (equal to the length of each of the constituent rows) substantially equal to the width over which the beam can be deflected laterally (e.g., 5 mm). Hence, in this example, each stripe has dimensions of 5xc3x9725 mm, representing an area that can be exposed by a single respective scanning motion of the wafer stage.
Development of the present invention began with consideration of a sequential scheme for exposing chips as shown in FIG. 31, in which the disposition of stripes is established so as to expose chips onto the wafer with minimal movement of the wafer stage, thereby improving throughput. Specifically, in FIG. 31, exposure of chips is performed in numerical order beginning with the upper left corner of the wafer W. Each chip has a unique number in FIG. 31. According to the exposure sequence, adjacent stripes are exposed wherever possible. Since the wafer W is round and each chip is rectilinear, it can be seen that some of the chips (notably the peripheral chips) are not located completely within the bounds of the wafer. Obviously, these peripheral chips cannot (and do not) become functional devices. Only the chips located entirely within the bounds of the wafer become xe2x80x9cfunctional-device chips.xe2x80x9d Nevertheless, the peripheral chips are included in the numerical order in which the chips are exposed on the wafer.
To maximize throughput and resolution, exposure of a wafer W as shown in FIG. 31 is performed using an electron beam accelerated by a high voltage and having high beam current. Consequently, the electron-beam energy locally absorbed by the wafer W in the region of a chip currently undergoing exposure is high. For example, with a beam subjected to an acceleration voltage of 100 kV and having a beam current of 25 xcexcA, the energy incident on the wafer is 2.5 W. This energy exceeds the incident energy otherwise applied in optical microlithography (using, e.g., a KrF excimer laser source) by a factor of 10 or more. At least about 80% of the incident energy is absorbed by the wafer and converted into heat, causing the wafer temperature to rise. Localized heating of the wafer causes the exposure positions on the wafer to shift laterally. Also, CPB microlithography is performed under sub-atmospheric pressure (xe2x80x9cvacuumxe2x80x9d). As a result, whereas some wafer heat is conducted to the wafer chuck, most of the wafer heat remains on the wafer, thereby accentuating the adverse effects of thermal expansion of the wafer.
In view of the shortcomings of the prior art, as summarized above, an object of the invention is to provide charged-particle-beam (CPB) microlithography methods exhibiting reduced net lateral shift of exposure position on the wafer caused by exposure-induced thermal expansion of the wafer.
To such end, and according to a first aspect of the invention, CPB microlithography methods are provided in which the sequence with which the wafer is exposed with chips (and with stripes in individual chips) is altered so as to reduce the net lateral shift of exposure position on the wafer caused by thermal expansion.
In combination with altering the exposure order, the wafer chuck can be provided with channels or the like through which a heat-transfer gas is conducted so as to contact the under-surface of the wafer as the wafer is being exposed. Hence, heat is better conducted away from the wafer during exposure.
In combination with any of the foregoing, the magnitude and direction of lateral shift of various regions of the wafer can be predicted in advance. This information can be used to apply deflectional corrections to the beam and/or positional corrections of the wafer stage to offset the lateral shift.
The foregoing aspects result in reduced deviations of exposure position caused by thermal expansion of the wafer, thereby increasing exposure accuracy and resolution.
The foregoing and additional features and advantages of the invention will be more readily understood from the following detailed description, which proceeds with reference to the accompanying drawings.